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Chapter 15: Arithmetic Library
Table 15–24 shows the Gain block I/O formats.
15–17
Table 15–24. Gain Block I/O Formats
(1)
,
I/O
Simulink
(2) (3)
VHDL
Type
I1[ L1].[R1]
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I
I2 [1]
I2: in STD_LOGIC
Implicit
(4)
I3 [1]
I3: in STD_LOGIC
O
O1 [L1 +
LK].2*max(R1,RK)]
(5)
O1: out STD_LOGIC_VECTOR({L1+LK+2*max(R1,RK)-1} DOWNTO 0)
Implicit
Notes to Table 15–24 :
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
(3) I1 [L].[R] is an input port. O1 [L].[R] is an output port.
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
(5) K is the gain constant with the format K [LK].[RK]
Figure 15–9 shows an example with the Gain block.
Figure 15–9. Gain Block Example
Increment Decrement
The Increment Decrement block increments or decrements a value in time. The output
is a signed integer, unsigned integer, or signed binary fractional number. For all
number formats, the counting sequence increases or decreases by the smallest
representable value; for integer types, the value always changes by 1.
Table 15–25 shows the Increment Decrement block inputs and outputs.
Table 15–25. Increment Decrement Block Inputs and Outputs
ena
sclr
c
Signal
Direction
Input
Input
Output
Description
Optional clock enable.
Optional synchronous clear.
Result.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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